Power management in conventional double data rate memory modules relies on discrete devices (i.e., a controller, voltage regulators, diodes and various passive components) implemented on a memory controller located on a host device (i.e., a motherboard). Power management performed by the memory controller would be shared for all of the memory modules. Conventional double data rate memory modules use of an I2C bus to report temperature sensor measurements to a host memory controller. Power measurements are not available for memory modules.
Integrating power measurement functionality into a single chip that is fully programmable would accommodate density scaling, power sequencing, voltage margining and storage class memory support. However, accessing power measurements on a conventional bus would be slow and can result in latency when there are bandwidth issues.
It would be desirable to implement a DDR5 PMIC interface protocol and operation.